Semiconductor Dynamic Random Access Memory (DRAM) devices have been applied in integrated circuits for many years. Indeed, a memory cell is provided for each bit stored by a DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. The source of the access transistor is connected to one terminal of the capacitor. The transistor gate electrode is connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Therefore, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
With the trend of making the semiconductor devices, the sizes of memory cells have gotten smaller and smaller. Thus, the area available for a single memory cell has become very small. This has caused a reduction in capacitor area, which in turn results in a reduction in cell capacitance. For very small memory cells, planar capacitor becomes very difficult to use reliably. Specifically, as the size of the capacitor decreases, the capacitance of the capacitor also decreases and the amount of the charge capable of being stored by the capacitor similarly decreases. This results in the capacitor being very susceptible to .alpha. particle interference. Additionally, as the capacitance decreases, the charges held by storage capacitor must be refreshed often.
Prior art approaches to overcome these problems have resulted in the development of various types of capacitor. One of the capacitors is honeycomb-shape capacitor structure. The process uses the characteristic that the oxidation rate at grain boundary is higher than that at the grain itself, and the oxide is thicker at the grain boundary. Then, an etching mask is formed over the grain boundary by etching process. Finally, the etching mask is used for generating the honeycomb-shape capacitor structure. However, the structure has a plurality of tips formed thereon, which will resulte leakage current in the structure. Please see "The Honeycomb-Shape Capacitor Structure for ULSI DRAM, S. Yu et al., IEEE Electron Device Lett., vol. 14, p.369, 1993" and "Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon, S. L. Wu et al., IEEE Electron Device Lett., vol. 14, p.379, 1993."
Further, a capacitor over bit line (COB) cell with a hemispherical grain silicon storage node has been developed (see "Capacitor Over Bit Line Cell With Hemispherical Grain Storage Node For 64 Mb DRAMs", M. Sakao et al., microelectronics research laboratories, NEC Corporation, IEDM Tech Dig., December 1990, pp655-658). The HSG-silicon is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous silicon to polycrystalline silicon. This memory cell provides about two times capacitance by increasing the effective surface area of a simple storage node. The following art teaches a highly selective etching method between HSG-silicon and polysilicon. Please see "Selective Etching Technology of in-situ P Doped Poly-Si (SETOP) for High Density DRAM Capacitors, S. H. Woo etal., 1994, Symposium on VLSI Technology Digest of Technical Papers". The present invention will use the method to form storage node of a capacitor.